1. Field of the Invention
The present invention relates to a synchronous oscillator for outputting clock signals, a clock recovery apparatus, a clock distribution circuit, and a multi-mode injection circuit.
2. Description of the Related Art
Recently, in the field of digital transmission, demands for transferring massive data at high speeds and with low power dissipation have been increasing. For the interface for this data transfer, clock recovery apparatuses are in wide use.
At the same time, the resistance against jitters is desired of high-speed interfaces due to the increased jitter components contained in signals caused by increased transfer rates.
The clock recovering includes those based on PLL application and the selection or generation of the clock of a phase locked with a reception data signal from a multi-phase clock signal.
However, these clock recovery schemes involve a problem that a high-speed operation requires a phase comparator operating at high speeds, thereby making it difficult to realize high-speed operations of clock recovery apparatuses.
In addition, because these schemes are realized depending on the negative feedback for locking with reception data signals, it takes relatively long for a clock signal to be synchronized with a reception data signal, thereby making these schemes unsuitable for the transfer of burst data that requires the locking with the reception data signal in a relatively short period of time.
Meanwhile, a clock recovery scheme based on a gated voltage controlled oscillator (hereafter referred to as a gated VCO) was proposed (refer to M. Banu and A. E. Dunlop; “Clock Recovery Circuits with Instantaneous Locking,” Electronics Letters, Vol. 28, No. 23, Nov. 1992, pp. 2127-2130, for example).
This scheme does not require a phase comparator, so that high-speed operation is not limited by such a device. This scheme also enables the instantaneous locking with a reception data signal.
Now, referring to FIG. 1, there is shown a schematic diagram illustrating one example of a general clock recovery scheme based on the gated VCO (refer to Japanese Patent Laid-open No. Hei 8-213979, for example).
FIGS. 2A through 2C show operation timings of an edge detector shown in FIG. 1.
A clock recovery apparatus 1 shown in FIG. 1 has an edge detector 2 and a voltage-controlled oscillator 3. The edge detector 2 has a delay circuit 21 and an exclusive-OR (EXOR) gate 22.
In the edge detector 2, a reception data signal rdt is entered.
In the edge detector 2, the reception data signal rdt is delayed by the delay circuit 21 and a resultant delay signal S21 is supplied to the EXOR gate 22. In the EXOR gate 22, an EXOR operation is executed on the entered reception data signal rdt and the delay signal S21 and a result thereof is outputted to the voltage-controlled oscillator 3 as a gating signal S2.
In the voltage-controlled oscillator 3, an oscillation frequency is controlled by an oscillation frequency control voltage fcv and a result clock signal S3 is outputted with a timing corresponding to the gating signal S2.